The present invention relates to a manufacturing process of a semiconductor device, and more particularly to a process of manufacturing a static induction type semiconductor device, such as a static induction transistor (SIT) and an integrated circuit involving the SIT.
Interest in a SIT or a SIT integrated circuit focuses on high frequency or high speed operation with a lower power consumption, and moreover its simple fabrication. On the other hand, to obtain better performance of the SIT devices, a microprocessing technique is also required. The problems to be solved in the manufacturing process for the conventional planar type SIT shown in FIG. 1 are mentioned below. FIG. 1 illustrates a unit of N channel SIT, and the following description is made for one unit which is used as a SIT in the almost SIT integrated circuits. FIG. 1(a) shows a sectional view, wherein a N epitaxial growth layer 3 and an oxide film on a N.sup.+ Si substrate (a source or a drain) 1, and a P.sup.+ gate region 4 is selectively diffused. The gate spacing i.e. the inner spacing between the P.sup.+ gate region 4 depends on an impurity concentration of the growth layer 3, the design whether the SIT is normally off or on, etc. In a logic circuit, the normally off type device is usually used where the gate spacing is chosen to be less than two times of a width of the depletion layer induced by a diffusion potential of a P.sup.+ N junction. In FIG. 1(b), a drain N.sup.+ region (or source region) 2 is formed by the selective diffusion of N-type impurity. Since it is preferable that the N.sup.- region lies between the N.sup.+ region 2 and the P.sup.+ region 4 to reduce the capacitance and to increase the break-down voltage, the small dimension of the window opened for the N.sup.+ selective diffusion is required with the higher positional accuracy. In FIG. 1(c), a metal evaporation is carried out after opening SiO.sub.2 windows of contacts, and the metal wiring is finished. The microprocessing technique is also required to open the contact window of the drain (or source) N.sup.+ region 2. In FIG. 1(d), the plane view of an accomplished SIT of one unit is illustrated, and the space between the metals such as the drain (or source) D(s) and the gate G will be narrower depending on the scale-reduction of the element. When the SIT fabricated simply as described above composes an injection type logic with a lateral PNP bipolar transistor (BJT), the logic operates with extremely low energy, i.e. about 2fJ/gate of the power-delay time product (P.multidot.t product). As obviously seen from FIG. 1(d), one way for improving the above described performance is to reduce the whole area or the undesired portion of the gate P.sup.+ region 4 and to furthermore minimize the N.sup.+ region 2.
FIG. 2 shows one example of the conventional construction for improving the above described drawbacks, and its construction is known as a step cut type SIT. In this case, the gate P.sup.+ region 4 is formed in the bottom of a stepped portion where a source series resistance is small in an inverted type SIT (in which the top of the stepped portion is used for the drain) as well as the capacitance because of a lengthened interval between the P.sup.+ region 4 and the N.sup.+ region 2. However the existance of the grooves prevents the N.sup.+ region 2 on the top of the stepped portion, the P.sup.+ region 4 in the bottom portion and the metal wiring from being sufficiently formed owing to the thickness distribution of the resist film or the gap between the mask and the exposed area.